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Time-Interleaved Analog-To-Digital Converters
Ethiopia Enideg Nigussie. Ebrahim Ghafar-Zadeh. Authors: Louwsma , Simon, van Tuijl , E. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration.
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The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.
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Interleaving ADCs: Unraveling the Mysteries | Analog Devices
However, when time-interleaving several ADCs, differences in gain and phase-response including time-skew as well as DC offset between the individual ADCs produce nonlinear distortion called aliasing that is typically the main performance limitation of time-interleaved ADC arrays. These differences are usually referred to as mismatch errors and are very challenging to remove by mere analog design and careful circuit layout.
It specifies the ratio between the amplitude of the fundamental and the strongest spurious signal. As can be seen, the unwanted aliasing spur levels differ between the different ADCs but common to all time-interleaved ADCs in general is the fact that effects of phase-response mismatches and time-skew grow worse with frequency.
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